The subject matter of this invention lies in the field of computers and specifically techniques of high speed memory addressing.
As newer generations of computers and computer technology evolve, the focus has primarily been on improving the quantity of information processed and the speed at which such information is handled. It is obvious that the quantity can always be increased by adding more hardware. Fortunately, system designers can avail themselves of newer, more compact, and more energy efficient technologies that render such increases feasible. To increase the speed or throughput of computer apparatus, however, one has to do more than just upgrade the hardware. Oftentimes it is not simply a matter of substituting faster hardware for slower hardware.
An examination of the various operations that occur within a computer indicates that some tasks will take longer to perform than others. Typically, data manipulation functions such as addition and subtraction require very little central processing unit (CPU) time. On the other hand, the time necessary to read data and instructions held in memory is much greater and is perhaps the most time-consuming activity encountered in the course of a computer's operation. During such memory operations, the CPU is forced to remain idle, lowering the overall efficiency of the computer. For that reason, methods for reducing memory access time using either hardware, or software, or a combination of the two, are continually being developed.
One method currently used is that of instruction look ahead. Look ahead techniques are conceptually very simple and perhaps not original with computer technology. Normally, instructions are stored sequentially in blocks in a memory. The method assumes that there is a high probability that the next instruction can be found at the next sequential location in memory. While one instruction is being fetched from the memory, the memory addressing circuitry selects the instruction located in the next sequential location, while the first instruction is utilized. At the conclusion of that operation, the CPU will select the second instruction immediately unless instructed to jump to a different location for a new block of instructions. Assuming that that second instruction is properly the next necessary step, it can be utilized without requiring a repositioning of the memory. At that time the look ahead circuitry accesses the third sequential location on the assumption that the instruction located therein will be requested at the conclusion of the current execution.
If there are few jumps required for access of instructions, the technique of look ahead can be quite advantageous. As the number of jumps increases, the benefit realized from look ahead diminishes proportionately. Assuming that instructions are stored sequentially in significantly large blocks in the memory, thus requiring few jumps, look ahead is a viable method for increasing the throughput of a computer system. Still, with the improved hardware, look ahead techniques as currently employed are unable to keep pace with the lightning-fast operations of the CPU. Thus, memory access time must be decreased even further.
A shortcoming of present look ahead techniques is the cost in terms of hardware and software. Contemporary systems require vast amounts of dedicated hardware and software in the CPU to achieve a look ahead capability. The actual configuration must be tailored to the individual requirements of each CPU, requiring a separate design in each instance. A universal, standalone module, external to the CPU would provide obvious savings.